A prior art flash memory device includes a memory array containing a large number of flash memory cells divided into a number of blocks. The voltage on each of the word lines is controlled by a word line driver to program, erase or read the memory cells in the respective row. FIG. 1 shows a block diagram of a circuit that includes one of several prior art word line drivers 301 that would normally be used in a row decoder (not shown) to couple one of several possible voltages to a respective word line 30. Thus, respective word line drivers 301 are provided for all of the word lines 30 in a block. Each word line driver 301a-301N includes several voltage nodes 312-328 that are coupled to receive a supply voltage having a respective magnitude. The voltage nodes 312-328 are coupled to the respective word line 30 through a switch 320 enabled in accordance with the operation of the selected row of memory cells. The switches 320 are NMOS transistors controlled by a high voltage shifter 310, such as a charge pump circuit (not shown) or by other means known to one skilled in the art. When enabled, the high voltage shifter 310 provides a voltage to turn ON the transistor switch 320 and couple the respective voltage nodes 312-328 to the selected word line 30. Additionally, each driver 301 includes a stand-by switch 362 and a voltage discharge circuit 364 coupled to the word line 30. The stand-by switch 362 is enabled when the memory block is inactive, and disabled when the memory block receives a command for a memory operation. The voltage discharge circuit 364, which conventionally includes a high impedance for causing any voltage capacitively stored on the respective word line 30, including voltage stored on capacitors coupled to the word line 30 such as a capacitor 315 (which is discussed further below), to be gradually discharged after a memory operation is complete to prepare for the next command.
The word line driver 301 includes a program block 302 to apply a programming voltage to one of the word line 30 selected for programming during a programming operation, a read block 306 to apply one of several read voltages to a word line 30 selected for reading during a read operation, and an enable block 304 to apply one of two enable voltages to a non-selected word line 30 during either a programming or reading operation. The program voltage supplied by the program block 302 must be sufficiently large to store charge on the floating gate when the selected memory cell is programmed. When the switch 320 is enabled, the program node 312 is coupled in series with a resistor 313 and a capacitor 315, which in combination act as a low pass filter 311 that filters the supplied voltage before the voltage is applied to the word line 30. The low pass filter 311 is used as a delay element to minimize disturbances due to word line-to-word line coupling when the signal applied to the word line 30 transitions to a high voltage level or a low voltage level. During the program operation, the enable block 304 applies a program enable voltage from the program enable node 314 to a respective one of the word lines 30 that is not selected for programming. As described above, a voltage sufficient to turn on all the unselected memory cells 14 must be applied to the word lines 30 of the other rows to program the selected row.
Similarly, during a read operation, the read block 306 applies a read voltage to a respective word line 30 that is selected for reading. Since the memory cell is capable of storing multiple bits of data at multiple levels of charge on its floating gate, several read voltages are made available through multiple bias voltage nodes 324-328. For example, since a 2-bit multilevel memory cell 14 may be programmed to one of four threshold voltage levels, three read voltages are used to read data from one of four possible states (0,0), (0,1), (1,0), (1,1). Bias voltage node A 324 may provide a voltage level for discriminating between states (0,0) or (0,1), the voltage level provided to the bias voltage node B 326 may be used to read states (0,1) or (1,0), and the voltage level provided to the bias voltage node C 328 may be used to read states (1,0) or (1,1). During the read operation, the enable block 304 applies a read enable voltage from the read enable node 316 to a respective one of the word lines 30 if the word line is not selected for reading to turn on the memory cells 14 of the non-selected rows as previously described.
As mentioned above, respective word line drivers 301 must be provided for all of the word lines 30 in a block. Therefore, for a block containing 32 rows of memory cells, 32 word line drivers 301 must be provided. The area on a semiconductor die that must be devoted to such word line drivers is further increased by the use of the multilevel memory cell in the flash memory block 10 since more voltage levels must be supplied by each of the word line drivers 301 as more bits are stored in the memory cells. Specifically, each additional voltage that is supplied requires an additional voltage node to incorporate in the word line driver 301 circuitry or by some other circuitry. Therefore, as the number of read voltages supplied to the select memory cells increases, each of the drivers 301 require additional circuitry. Therefore, the memory chip must accommodate a greater number of the larger drivers 301, resulting in a much larger die size. For example, the word line driver 301a shown in FIG. 1 requires 7 transistors 320, 1 low-pass filter 311, 6 high voltage shifters 310 and 1 voltage discharge circuit 364. A block of memory cells having 32 rows would therefore require 224 (7*32) transistors 320, 7 low-pass filters 311, 192 (6*32) high voltage shifters, and 7 voltage discharge circuits 364. This large number of components can require a significant amount of area on a semiconductor die, thus increasing the cost of non-volatile memory devices having row decoders that use the word line drivers 301.
There is therefore a need for a non-volatile memory device and method that reduces the circuit size of the word line drivers 301 to reduce the overall die size of the memory chip.